HDL Technical Team Lead

Company: Mj3 Partners, Inc.
Location: Boulder
Posted on: February 18, 2026

Job Description:

Job Description Job Description Our client is a fast-growing, privately owned company that develops high-performance antenna and RF system products that are used across defense and aerospace applications. Summary Our client is looking for an HDL Technical Team Lead to guide and elevate their FPGA/HDL development efforts across multiple advanced RF programs. This role is ideal for a senior HDL engineer who enjoys technical leadership, system-level thinking, and influencing how teams build, without direct people management responsibilities. You will serve as the technical lead across 3-4 concurrent programs , providing architectural guidance, ensuring consistency and reuse across designs, and helping teams make sound engineering tradeoffs. While approximately 25% of your time will be hands-on (including specialty tooling and targeted development), the majority of the role is strategic and coordination-focused - driving technical direction, alignment, and execution across projects. This is a high-impact role for someone who enjoys leading through expertise, mentoring by example, and shaping how systems come together at scale. What You’ll Do Serve as the technical lead for HDL development across multiple concurrent programs Guide system-level HDL architecture and ensure designs align with program requirements and long-term platform strategy Identify opportunities to reuse architectures, IP, and tooling across projects to improve efficiency and consistency Lead technical planning, design reviews, and cross-team alignment — ensuring teams move quickly without sacrificing quality Spend ~25% of your time on specialty tooling, targeted HDL development, and complex problem-solving Collaborate closely with RF, embedded software, and hardware teams to ensure seamless system integration Support and mentor HDL engineers through technical guidance, design feedback, and best-practice development — without direct people management Own and influence design documentation, simulation strategy, verification approach, and integration readiness Evaluate architectural trade-offs, interfaces, and timing constraints across systems and programs Support hardware bring-up and integration efforts in Linux-based environments AAP/EEO Statement Our client is an Equal Employment Opportunity employer committed to providing equal opportunity in all of their employment practices, including selection, hiring, assignment, re-assignment, promotion, transfer, compensation, discipline, and termination. The Company prohibits discrimination, harassment, and retaliation in employment based on race; color; religion; genetic information; national origin; sex (including same sex); sexual orientation; gender identity; pregnancy, childbirth, or related medical conditions; age; disability or handicap; citizenship status; service member status; or any other category protected by federal, state, or local law. They support protected veterans and individuals with disabilities through their affirmative action program.Bottom of Form Requirements Qualifications Required Education and Experience U.S. Citizenship and ability to obtain a U.S. Security Clearance Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field (Master’s preferred) 3 years of FPGA / HDL development experience (Verilog, VHDL, or similar) Experience leading or owning technical direction for HDL designs or projects Strong understanding of digital system design, timing constraints and interfaces Experience with high-speed and control interfaces (PCIe, SPI, I2C, AXI, Aurora, JESD, etc.) Familiarity with RF system concepts and how digital logic interfaces with analog hardware Ability to think across systems and programs, not just individual blocks Preferred Experience Python, C/C++, or other languages used for test, tooling, or automation Linux development experience (user space, device drivers, Yocto, Petalinux) Simulation and verification tools (Vivado, ModelSim, etc.) Hardware exposure including board bring-up, lab debug, or schematic review Experience with modeling or HDL generation tools (e,g., Spade, Veryl) Prior experience supporting multiple programs or product lines simultaneously Other Duties Please note this job description is not designed to cover or contain a comprehensive listing of activities, duties or responsibilities that are required of the employee for this job. Duties, responsibilities, and activities may change at any time with or without notice. Supervisory Responsibility This position has no direct supervisory responsibilities. Position Type/Expected Hours of Work This is a full-time position at 40 hours per week. Typical office hours include Monday-Friday, 8:00am-4:30pm; however, these hours may vary based on workload and the manager’s discretion. Travel About 10% travel is expected for this position. Physical Demands While performing the duties of this job, the employee is regularly required to talk or hear. Specific vision abilities required by this job include close vision and ability to adjust focus. This would require the ability to lift files, open filing cabinets, and bend or stand on a stool as necessary. The employee will also regularly be seated at a desk and using a computer. Reasonable accommodations may be made to enable individuals with disabilities to perform the essential functions. Benefits Benefits Summary Our client offers all employees four weeks of PTO each year, flexible scheduling, hybrid work, tuition reimbursement, up to 6% 401(k) match, and healthcare, dental, and vision plans.

Keywords: Mj3 Partners, Inc., Westminster , HDL Technical Team Lead, Engineering , Boulder, Colorado